The present invention relates generally to integrated circuits, and more particularly, to a scan flip-flop circuit.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital and sometimes analog components on a single chip. ICs may have manufacturing defects such as physical failures and fabrication defects that cause the ICs to malfunction. Thus, the ICs need to be tested to detect manufacturing defects. Design for test (DFT) techniques add testability features to ICs that allow automatic test equipment (ATEs) to execute various fault tests using test patterns generated by an automatic test pattern generator (ATPG) on the ICs to identify manufacturing defects. ICs undergoing testing are referred to as circuits-under-test (CUT).
Conventional fault tests can be categorized as two types—functional testing and structural testing (also referred to as scan-based testing). Functional testing technique use mathematical models to simulate manufacturing defects and test an IC. However, due to the increasing complexity of ICs, generating such mathematical models has become increasingly difficult. Structural testing techniques are robust techniques that do not require sophisticated mathematical models to detect manufacturing defects. Instead, the manufacturing defects are modeled as logic faults that can be detected using simple memory elements such as flip-flops. Generally, ICs that undergo fault testing include multiple scan flip-flops that form a scan-chain and then test data is shifted in one end of the scan chain and out the other with the starting data compared to the shift out data to detect any faults.
Structural testing includes various fault models such as stuck-at fault, transition fault and path delay fault models. The stuck-at fault model is used to detect faulty connections between circuit elements that cause the CUT to be stuck at a particular logic state. The transition fault model is used to detect a failure of state transition at a particular element of the CUT that propagates through the CUT within a specific time period. The path delay fault model calculates a sum of delays at each element in a path within the CUT and detects faults by comparing the sum of delays of the path with a delay of a critical path.
Fault test methods that use the transition fault model require a test pattern pair (V1, V2) that are vectors to be applied to the CUTs by way of the scan flip-flops of the scan chain. The scan flip-flops function as a gateway to test the CUTs and an observation point to observe the test results of the CUTs. During an initialization cycle, the test pattern V1 is applied to the scan flip-flops at an initialization clock pulse to initialize the CUT to a first logic state. During a launch clock cycle, the test pattern V2 is applied (launched) as a test input to the scan flip-flops. The scan flip-flops receive a scan enable signal from a tester (i.e., ATE). When the scan enable signal transitions from high to low, the scan flip-flops receive the test pattern V2 as input at a launch clock pulse. The test pattern V2 initiates state transitions from the first logic state to a second logic state. During a capture clock cycle, the logic state transitions are captured by the scan flip-flops at a capture clock pulse. The scan enable signal then transitions from low to high. The time period between the launch and capture clock pulses, during which the test pattern V2 is applied is referred to as an application period. Typically, the application period is equivalent to the time period when the IC operates at a maximum clock speed. This is referred to as at-speed testing. Thus, the launch and capture clock pulses are a pair of at-speed clock pulses. At-speed testing is important to ensure that the CUT operates correctly even at high clock speeds.
Based on the transition timing of the scan enable signal from high to low while launching the test patterns, fault test methods that use transition fault models can be categorized into two methods—launch-on-shift (LOS) and launch-on-capture (LOC).
In the LOS method, the scan enable signal is set to the logic low state during a positive edge of a last shift clock pulse, which is the last shift cycle of the scan flip-flop. Thus, the last shift clock pulse is the launch clock pulse. The result of the LOS method is captured at the subsequent at-speed clock pulse that is the capture clock pulse. ATPGs used to generate test patterns for the LOS method are referred to as combinational ATPGs. The combinational ATPGs require less time and a simple vector matrix to generate the test patterns that detect the faults in the CUT. Further, the combinational ATPGs do not include any memory elements.
In the LOC method, the transition of the scan enable signal from the logic high to the logic low state is independent of the launch clock pulse of the scan flip-flop. When the scan enable signal is low, the pair of at-speed clock pulses (launch and capture clock pulses) is applied to initiate the logic state transitions and capture the fault test results at the scan flip-flops. The ATPGs used to generate the test patterns for the LOC method are referred to as sequential ATPGs. A sequential ATPG searches for a sequence of test patterns that allow detection of a particular fault. As a result, sequential ATPGs require more time and a complex vector matrix to generate test patterns. Since a sequence of test patterns is used for fault detection, the sequential ATPGs include memory elements.
The LOS method provides high fault coverage and requires fewer test patterns than the LOC method. Since LOS requires fewer patterns, testing time for LOS is less than the test time using LOC. However, LOS requires the scan enable signal to switch at-speed, i.e., transition from the high to low at the maximum clock speed of the IC. Thus, the scan enable signal needs to be timed at a high functional frequency of the maximum clock speed. Further, since the scan enable signal is fanned out to each scan flip-flop of the scan chain, a large number of buffers and signal boosters are required to meet the timing requirement of the scan enable signal. Thus, timing criticality is introduced into the design of the scan flip-flop that results in an increase in area and power consumption of the IC.
Tester pads that generate the scan enable signal do not support high frequency signals and hence, generating a scan enable signal that is capable of switching at-speed is difficult. Further, the switching of the scan enable signal needs to be synchronized with the last shift clock pulse of the scan flip-flop. As a result, the testing procedure needs to be timed to ensure synchronization between the switching of the scan enable signal and the last shift clock pulse (launch clock pulse). These limitations increase the effort required when using LOS.
FIG. 1A is a schematic block diagram of a conventional scan flip-flop circuit 100 used for LOS testing. The scan flip-flop circuit 100 includes pipeline and scan flip-flops 102 and 104 and an OR gate 106. The pipeline flip-flop 102 has a data input terminal that receives a scan enable signal (SEN) from a scan enable port (SEN_port), which is a tester pad, a clock input terminal that receives a clock signal (CLK), and a data output terminal that generates a scan enable pipeline signal (SEN_pipeline). A first input terminal of the OR gate 106 is connected to the data input terminal of the pipeline flip-flop 102 for receiving the scan enable signal (SEN) and a second input terminal of the OR gate 106 is connected to the data output terminal of the pipeline flip-flop 102 for receiving the scan enable pipeline signal (SEN_pipeline). The OR gate 106 outputs a local scan enable signal (SEN_local). The scan flip-flop 104 has a first data input terminal (D) connected to circuits under test (not shown) to receive fault test results, a second data input terminal (SD) that receives test patterns from an ATE (not shown), a scan enable terminal (SE) connected to the output terminal of the OR gate 106 to receive the local scan enable signal (SEN_local), a clock input terminal that receives the clock signal (CLK), and a data output terminal (Q) connected to the circuit under test to output at least one of the received test patterns and the fault test results based on a logic state of the local scan enable signal (SEN_local).
FIG. 1B is a timing diagram that illustrates the scan enable (SEN), scan enable pipeline (SEN_pipeline) and local scan enable (SEN_local) signals of the scan flip-flop circuit 100. A plurality of clock pulses that include first through third clock pulses 108-112 are generated from T0-T3. The first and second clock pulses 108 and 110 are penultimate shift and last shift clock pulses, respectively, of the scan flip-flop circuit 100. The second and third clock pulses 110 and 112 form a pair of at-speed clock pulses, i.e., launch and capture clock pulses 110 and 112. At time T0, the scan enable (SEN), scan enable pipeline (SEN_pipeline) and local scan enable (SEN_local) signals are at logic high states. Time period T0-T1 is the initialization cycle and the CUTs are initialized using the test pattern V1 at the first clock pulse 108. At the end of the initialization cycle, the ATE sets the scan enable signal (SEN) to the logic low state asynchronously. Time period T1-T2 corresponds to the launch cycle. The scan enable pipeline signal (SEN_pipeline) remains high until the launch clock pulse 110 is received at the scan flip-flop circuit 100. Therefore, the OR gate 106 generates a logic high local scan enable signal (SEN_local) until the positive edge of the second (launch) clock pulse 110. At the positive edge of the launch clock pulse 110, the pipeline flip-flop 102 shifts the logic low scan enable signal (SEN) out as a logic low scan enable pipeline signal (SEN_pipeline). The OR gate 106 receives the logic low scan enable signal (SEN) and the logic low scan enable pipeline signal (SEN_pipeline) and generates a logic low local scan enable signal (SEN_local). The scan flip-flop 104 receives the logic low local scan enable signal (SEN_local) and initiates the state transition of the CUTs based on the test pattern V2 received at the second data input terminal of the flip-flop 104. Thus, the scan flip-flop 104 receives the local scan enable signal (SEN_local) that is synchronized with the launch clock pulse 110. However, this technique requires an increased routing awareness of the CUTs for the insertion of the pipeline flip-flop 102 before the scan flip-flop 104, which complicates the design process. Further, due to insertion of the pipeline flip-flop 102, the scan flip-flop circuit 100 is susceptible to noise glitches from the ATE (not shown) or from within the IC itself and due to crosstalk. Therefore, the timing requirement of the local scan enable signal (SEN_local) may not be met or may be met marginally, which may result in silicon failures across voltage and temperature variations leading to yield loss for the LOS method. Thus, the test result of the LOS method is not deterministic and may include errors.
Therefore, it would be advantageous to have a scan flip-flop circuit that allows CUTs to be tested using LOS independent of the type of ATPG.